1. Field of the Invention
The invention relates to a semiconductor and a method of fabricating the same, and more particularly to a wiring layer made of metal such as gold and a method of fabricating the same.
2. Description of the Related Art
As semiconductor elements become smaller, it is absolutely necessary to use a multi-layer wiring structure. An interlayer insulating film for a semiconductor device having such a multi-layer wiring structure, may include an insulating film made of silicon dioxide having a small dielectric constant and uniform quality for reducing parasitic capacitance between an upper wiring layer and a lower wiring layer or between wirings in a common wiring layer.
Further, as semiconductor elements become smaller, a width of wirings in a lower wiring layer and a spacing between adjacent wirings in a wiring layer are smaller. However, a wiring is required to have a cross-sectional area greater than a certain value in order to avoid increasing wiring resistance. As a result, an aspect ratio of the wiring defined by a thickness of the wiring divided by a width of the wiring, and an aspect ratio between wirings defined by a thickness of the wiring divided by a spacing between the wiring and an adjacent wiring both increase. In addition, it is required to planarize a surface of an interlayer insulating film which covers a lower wiring layer. If there were a large step at a surface of an interlayer insulating film, it would not be possible to form a fine photoresist pattern because of shortage of a focus margin in photolithography, when an upper wiring layer is formed on such an interlayer insulating film. The large step would bring problems of breakage of an upper wiring layer and generation of etching residue of material of which an upper wiring layer is made. For those reasons, an interlayer insulating film to be formed covering a lower wiring layer is required to have a flat surface.
In addition, when an interlayer insulating film is formed covering a wiring layer made of aluminum, a temperature at which an interlayer insulating film is formed has to be equal to or smaller than about 450.degree. C., which is a melting point of aluminum.
Bias sputtering and chemical vapor deposition (CVD) employing bias ECR may be used to form an interlayer insulating film for a multi-layer wiring structure made of aluminum or similar metal. The bias sputtering and bias ECR CVD correspond to improved sputtering and ECR plasma. According to the bias sputtering and bias ECR CVD techniques, projections of an interlayer insulating film which are formed simultaneously with deposition of an interlayer insulating film are cut off by virtue of a bias voltage. Thus, an interlayer insulating film is planarized at its upper surface.
However, bias sputtering and bias ECR have a problem that an interlayer insulating film formed on a wiring having a narrow width can be readily planarized, but an interlayer insulating film formed on a wiring having a wide width is quite difficult or impossible to planarize.
The above mentioned problem is explained hereinbelow in detail with reference to FIGS. 1 and 2. FIG. 1 is a plan view of a wiring layer constituted of three wirings 103, 104 and 105, and FIG. 2 is a cross-sectional view taken along the line II--II in FIG. 1.
As illustrated in FIG. 1, there are formed three wirings 103, 104 and 105 on a silicon substrate. Specifically, as illustrated in FIG. 2, a first interlayer insulating film 102 is formed on a silicon substrate 101, and the wirings 103, 104 and 105 are formed on the first interlayer insulating film 102. The wirings 103, 104 and 105 make a wiring layer. The wirings 103, 104 and 105 have a common thickness, but have different widths. That is, the wiring 104 is greater than the wiring 103 in width, and the wiring 105 is greater than the wiring 104 in width.
A second interlayer insulating film 106 is formed on the wirings 103 to 105 by bias sputtering or bias ECR-CVD so that the second interlayer insulating 106 fully covers the wirings 103 to 105. As illustrated in FIG. 2, the second interlayer insulating film 106 has a completely flat surface above the wiring 103 having the smallest width among the wirings. In contrast, there is produced a triangular projection 107a at a surface of the second interlayer insulating film 106 above the wiring 104 having a width greater than that of the wiring 103. Similarly, there is produced a trapezoidal projection 107b at a surface of the second interlayer insulating film 106 above the wiring 105 having a width much greater than that of the wiring 103.
As mentioned earlier, bias sputtering and bias ECR-CVD are quite useful for forming an interlayer insulating film, when there is fabricated a semiconductor device having a multi-layer wiring structure. However, when an interlayer insulating film is formed by those methods, it would be quite difficult to planarize the interlayer insulating film above wirings having a wide width, as having been explained with reference to FIGS. 1 and 2.
As a result, when an upper wiring layer is formed on an interlayer insulating film as the film 106 illustrated in FIG. 2, the upper wiring layer may be broken or may have an undesirable pattern. Such a problem is more remarkable, as a multi-layer wiring structure is made smaller in size.
In addition, if a through hole is intended to form throughout such an interlayer insulating film as the film 106 illustrated in FIG. 2, it is often impossible to form a through hole passing through projections formed on an interlayer insulating film, such as the triangular projection 107a and the trapezoidal projection 107b illustrated in FIG. 2.
One of solutions to the above mentioned problems has been suggested in Japanese Unexamined Patent Publication No. 2-22843 published on Jan. 25, 1990. The Publication suggests a semiconductor device comprising a semiconductor substrate, a first electrode or wiring formed on the substrate, an interlayer insulating film formed over the first electrode or wiring, and a second wiring formed on the interlayer insulating film, the second wiring being in electrical connection with the first electrode or wiring through a contact hole, characterized by a split pattern contact through which the first electrode or wiring makes contact with the second wiring.
However, the above mentioned Publication does not fully overcome the problems as mentioned above.